1. Field of the Invention
The present invention relates to the structure and process for fabricating semi-conductor devices and particularly Self-Aligned Schottky Metal Semi-Conductor Field Effect Transistors with buried source and drains (SASMESFETBUS) in the Y-coordinate.
2. Prior Art
In the past, SASMESFET's were accomplished by an etching step that defined source-drain-gate separations as described in the IEEE proceedings, Vol. 59, pp. 1244-5, August 1971, or facet-growth where epitaxial growth defined the channel as described in the U.S. Pat. No. 3,943,622, March 1976. Both of the above, even with the use of self-aligning as is the former, use processes that are relatively difficult to control thus structure geometries approaching anything like VLSI cannot be very small without sacrificing yield. Thus, the operating frequency is not as high, and series resistance is not as relatively low as might be desired. As such, there existed a need for a high-speed SASMESFET structure and process therefor that was process controllable at the desired relatively high operating frequency and low series resistance, yet have a reasonable yield in mass quantities.
U.S. Pat. No. 4,128,439 described a process for a MOSFET having buried source and drain. It will be appreciated that this is a MOSFET with no Schottky gate. Although ion implantation is used, subsequent electrical activation is provided by out-diffusion via thermal annealing which spreads the ion implanted area until it actually contacts the gate. It will be appreciated that since spatial spacings here are not critical, relatively imprecise thermal annealing may be used.